Semiconductor device and manufacturing method for same

ABSTRACT

A semiconductor device in which semiconductor chip(s) is or are mounted onto substrate(s) incorporating patterned wiring and the entirety or entireties has or have been sealed with resin(s), wherein by forming electrically conductive pattern(s) for shielding at end face(s) at top(s) of substrate(s) and attaching such electrically conductive pattern(s) to region(s) of ground plane pattern(s) on circuit board(s) of apparatus(es) which is or are provided with such semiconductor device(s), it is possible to shield semiconductor device(s) even without use of shield case(s). In such case, by applying material(s) possessing good shielding characteristics, e.g., gold plating, over electrically conductive pattern(s), it is possible to increase sensitivity with respect to electromagnetic noise and improve shielding effect (anti-electromagnetic-noise effect).

BACKGROUND OF INVENTION

[0001] This Nonprovisional application claims priority under 35 U.S.C.§119(a) on patent Application No. 2003-060083 filed in Japan on Mar. 6,2003, the entire contents of which are hereby incorporated by reference.

[0002] The present invention pertains to a semiconductor device that maybe used for sensors and/or for data communications which make use oflight, and to a manufacturing method for same. More particularly, thepresent invention pertains to a semiconductor device that may be used inan infrared communication device, and to a manufacturing method forsame.

[0003] Referring to FIG. 7, a manufacturing method for a conventionalsemiconductor device, e.g., an infrared communication device, will bedescribed.

[0004] First, substrate 101 is prepared, a plurality of fieldscontaining patterned wiring, not shown, being formed horizontally andvertically thereon; light emitting diode chips, photodiode chips, ICchips, and/or other such semiconductor chips, not shown, areincorporated into the respective patterned wiring fields of substrate101, being mounted thereon by means of die bonding, wire bonding, and/orthe like; and by thereafter using resin to mold the entirety of eachtogether with a light-emitting lens portion and a light-receiving lensportion, a plurality of semiconductor device blocks (semiconductordevice units) A, A, . . . are formed horizontally and vertically. Suchstate of affairs is shown in FIG. 7, the lines shown as dashed lines inthe drawing being horizontal and vertical dicing lines. A drill or thelike is thereafter used to form circular through-holes 102, 102, . . .in parallel fashion with respect to the vertical dicing lines, atlocations for forming terminals at respective semiconductor deviceblocks A, A, . . . ; copper plating is applied to the insidecircumferential surfaces of these through-holes 102, 102, . . . ; andthe substrate is then cut vertically and horizontally along the dicinglines. As a result, a semiconductor device of shape as shown in FIG. 8is formed.

[0005]FIG. 8(a) is a plan view of an infrared communication device asviewed from above. FIG. 8(b) is an oblique view of the bottom of aninfrared communication device as viewed from the back. Note that, atFIG. 8(a), reference numeral 103 is the molded resin portion, referencenumeral 104 is the light-emitting lens portion, and reference numeral105 is the light-receiving lens portion.

[0006] Furthermore, FIG. 9 shows a situation in which shield case 107 isattached by way of adhesive 106 to the top face of substrate 101 of theinfrared communication device constituted as described above. Note,however, that FIG. 9 is drawn such that it is possible to see throughshield case 107 attached thereto and view the features therebelow.

[0007] Infrared communication devices (hereinafter referred to simply as“device(s)”) of such construction may be used in a wide variety ofapplications—e.g., personal computers, PDAs, and printers—in opticaland/or wireless communication fields where data communication isinvolved. However, regardless of the product in question, the device isnever used on its own, infrared communication instead being but onefunction which is always incorporated into some apparatus or the other.That is, because the infrared communication device is installed withinan apparatus, the problem has existed that communications carried out bythe device can be affected by interference due to electromagnetic noisewhich is generated by the apparatus itself and/or electromagnetic noisefrom the exterior (e.g., mobile telephones, household appliances, andother such products which generate electromagnetic waves, and so forth).For increasing ability to withstand such electromagnetic noise,conventional strategies have therefore increased resistance toelectromagnetic noise by shielding the device as a result of enclosingsame within a shield case (see, e.g., Japanese Patent ApplicationPublication Kokai No. 2001-127310) or by addingelectromagnetic-noise-resisting circuitry to the IC circuitry.

[0008] Furthermore, as customers demand smaller sizes and lower profilesin media requiring infrared communication (primarily personal computers,PDAs, and other such information terminal equipment and so forth),decreases in device size have necessitated strategies such aselimination of the shield case and reduction in terminal surface areathrough reduced terminal pitch, despite the fact that the environmentwith respect to electromagnetic noise within the media is more stringentthan was the case conventionally.

[0009] Thus, the trend toward reduced infrared communication device sizehas in fact caused decreased resistance to electromagnetic noise asresult of elimination of the shield case despite the fact that there ismore need than was the case conventionally to increase resistance toelectromagnetic noise, resulting in abnormal operation of the device andpreventing reliable communication. Especially with the recent increasesin data communication speeds, the effects of noise can no longer beignored.

[0010] Furthermore, whereas the presence of the shield case hadconventionally provided some basis for acceptable antinoisecharacteristics, the recent proliferation of mobile telephones hasbrought a further steady worsening of the environment with respect toelectromagnetic noise, to the point where the mere inclusion of a shieldcase can no longer be considered to be a completely acceptable strategy.Furthermore, where a shield case had been provided, in the devicedisclosed at the aforementioned Japanese Patent Application PublicationKokai No. 2001-127310—like the infrared communication device shown inFIG. 9—the shield case was merely attached by adhesive to the device,the absence of any provision for establishing electrical continuity withthe device necessitating that terminal(s) be provided for connecting toground. And this has resulted in the problem that it has caused thedevice itself to increase in size.

[0011] Furthermore, with respect to the other strategy for dealing withelectromagnetic noise, i.e., adoption of a constitution in whichelectromagnetic-noise-resisting circuitry is added to the IC circuitry,because this causes considerable increase in the number of circuitelements as well as increased IC chip surface area, the concomitantincrease in cost and increase in device dimensions have been problems.

[0012] Moreover, with respect to the increased mounting strengthrequired to mount the device terminal portion to the apparatus circuitboard, the diameter of terminal through-holes 102 formed at substrate101, as shown in FIG. 8(b), has conventionally been made small,increasing the surface area available for adhesion by solder. Butdecreased diameter at through-holes 102 has placed demands on dicingprecision, such that in practice any displacement and/or stressesresulting therefrom has caused disappearance of terminals and/or peelingof copper foil from the end face thereof, resulting in defective productand leading to increases in cost due to lowered yield.

[0013] The present invention was conceived in order to solve suchproblems, its object being to provide a semiconductor device permittingimproved performance with respect to electromagnetic noise while at thesame time accommodating reduction in device size as well as profile, anda manufacturing method for same.

SUMMARY OF INVENTION

[0014] In accordance with one or more embodiments of the presentinvention, a semiconductor device in which one or more semiconductorchips have been mounted onto one or more substrates incorporatingpatterned wiring and the entirety has been sealed with one or moreresins is such that one or more electrically conductive patterns forshielding is or are formed at one or more end faces at the top of atleast one of the substrate or substrates. Here, at least one of theelectrically conductive pattern or patterns may formed from copper foil.In this way, by forming electrically conductive pattern(s) for shieldingat end face(s) at top(s) of substrate(s) and attaching such electricallyconductive pattern(s) at region(s) of ground plane pattern(s) on circuitboard(s) of apparatus(es) which is or are provided with suchsemiconductor device(s), it is possible to shield semiconductordevice(s) even without use of shield case(s). In such case, by applyingmaterial(s) possessing good shielding characteristics, e.g., goldplating, over copper foil, it is possible to increase sensitivity withrespect to electromagnetic noise and improve shielding effect(anti-electromagnetic-noise effect).

[0015] Furthermore, one or more shield cases may be attached over atleast one of the electrically conductive pattern or patterns by way ofone or more intervening electrically conductive adhesives. In such acase, at least one surface of at least one of the shield case or casesmay be plated with gold. This will permit further improvement inshielding effect. Furthermore, application of gold plating will make itpossible to prevent occurrence of degradation in characteristics due tothe effects of contact resistance and/or occurrence of solder defectsdue to copper foil surface oxidation.

[0016] Furthermore, in the event that gold plating is applied to shieldcase(s), and/or in the event that gold plating is applied toelectrically conductive pattern(s), silver paste may be applied toelectrically conductive pattern(s) before attaching shield case(s). Dueto compatibility between silver paste and gold plating, this makes itpossible to improve adhesive strength.

[0017] Furthermore, in accordance with one or more embodiments of thepresent invention, a semiconductor device in which one or moresemiconductor chips have been mounted onto one or more substratesincorporating patterned wiring and the entirety or entireties has orhave been sealed with one or more resins is such that one or moreelectrically conductive patterns is or are formed at one or more endfaces at the bottom of at least one of the substrate or substrates; andat least as many terminal or terminals of such number, size, and shapeas is or are sufficient for connection to the patterned wiring is or areformed by using one or more dies to blank out at least one region at orin the vicinity of at least one of the electrically conductive patternor patterns. By thus using die(s) to blank out and shape terminalregion(s), copper foil can be formed at terminal end face(s), andbecause the surface area of that copper foil can be made greater thanthe surface area of copper foil at terminal end face(s) in semiconductordevice(s) of conventional structure, it is possible to improve mountingstrength with respect to apparatus circuit board(s).

[0018] Here, by causing shape(s) of terminal(s) to be formed so as to berectangular in cross-section and so as to protrude to the exterior, itis possible when mounting semiconductor device(s) to circuit board(s) ofapparatus(es) to achieve mounting such that there is good positionalaccuracy during reflow mounting due to self-alignment effect resultingfrom positional displacement.

[0019] Furthermore, a semiconductor device manufacturing method inaccordance with one or more embodiments of the present inventioncomprises forming a plurality of patterned wiring fields horizontallyand vertically on one or more substrates, at least one of the fieldscontaining patterned wiring for connection to one or more semiconductorchips; mounting at least one of the semiconductor chips or chips to atleast one of the patterned wiring fields; causing same to undergo diebonding and/or wire bonding and then sealing the entirety of at leastone of the mounted semiconductor chips or chips with one or more resins;thereafter forming at least one vertically long set of at least twothrough-holes in more or less parallel fashion with respect to at leastone region at or in the vicinity of at least one end face at at leastone side corresponding to at least one top and with respect to at leastone region at or in the vicinity of at least one end face at at leastone side corresponding to at least one bottom of each of at least one ofthe semiconductor chip or chips; applying plating to at least a portionof the interior of at least one of the through-hole or through-holes;forming one or more electrically conductive patterns; thereafter usingone or more dies to blank out and shape at least one region at or in thevicinity of at least a portion of the through-holes and containing atleast one region at or in the vicinity of at least one of theelectrically conductive pattern or patterns formed in at least oneregion at or in the vicinity of at least one of the end face or faces atat least one of the side or sides corresponding to at least one of thebottom or bottoms of at least one of the semiconductor chip or chips soas to form one or more electrically conductive patterns for shielding ator in the vicinity of at least one of the end face or faces at at leastone of the side or sides corresponding to at least one of the top ortops of at least one of the semiconductor chip or chips, and so as toform at least as many terminal or terminals of such number, size, andshape as is or are sufficient for connection to the patterned wiring atat least one region at or in the vicinity of at least one of the endface or faces at at least one of the side or sides corresponding to atleast one of the bottom or bottoms of at least one of the semiconductorchip or chips; and thereafter cutting in one or more directionsperpendicular to at least one of the vertically long set or sets ofthrough-holes so as to divide substantially the entirety into aplurality of individual semiconductor devices.

[0020] Because manufacturing method(s) in accordance with embodiment(s)of the present invention make it possible to form electricallyconductive pattern(s) for shielding at or in the vicinity of end face(s)at side(s) corresponding to top(s) of semiconductor chip(s) simultaneouswith preparation of individual semiconductor device substrate(s), aftercarrying out dicing and dividing the entirety into individual units, itis possible, by attaching electrically conductive pattern(s) formed atend face(s) of such semiconductor device(s) to region(s) of ground planepattern(s) formed on circuit board(s) of apparatus(es), to shieldsemiconductor device(s) even without use of shield case(s). Furthermore,by using die(s) to blank out and form terminal(s) into special shape(s)during formation of end face(s) at bottom(s) of semiconductor chip(s),because greater copper foil surface area can be attained at terminal endface(s) than was the case conventionally, it is possible to increasemounting strength with respect to apparatus circuit board(s).

[0021] In such case, shield case(s) may, by way of interveningelectrically conductive adhesive(s), be attached to electricallyconductive pattern(s) for shielding formed at or in the vicinity of endface(s) at side(s) corresponding to top(s) of semiconductor chip(s).Thus, because adhesive attachment of shield case(s) to electricallyconductive pattern(s) at semiconductor device(s) eliminates the need forshield case terminal(s) for connecting shield case(s) to ground at theoutside thereof, reduction in shield case size is made possible; andmoreover, it is also possible to reduce or eliminate such problems asmounting defects caused by lifting of shield case(s) during mounting ofsemiconductor device(s) to circuit board(s).

BRIEF DESCRIPTION OF DRAWINGS

[0022]FIG. 1 is a plan view, as viewed from above, of a semiconductordevice in accordance with the present invention.

[0023]FIG. 2 is an oblique view, as viewed from the back, of the bottomof a semiconductor device in accordance with the present invention.

[0024]FIG. 3 is a plan view, as viewed from above and drawn such that itis possible to see through the top and view the features therebelow,showing how a shield case is attached to a semiconductor device inaccordance with the present invention.

[0025]FIG. 4 is a partial enlarged view of the tip portions of terminalsin a semiconductor device in accordance with the present invention.

[0026]FIG. 5 contains process drawings for describing a method ofmanufacturing a semiconductor device in accordance with the presentinvention.

[0027]FIG. 6 contains process drawings for describing a method ofmanufacturing a semiconductor device in accordance with the presentinvention.

[0028]FIG. 7 is a process drawing to assist in describing a method ofmanufacturing a semiconductor device in accordance with the conventionalart.

[0029]FIG. 8(a) is a plan view of a conventional semiconductor device asviewed from above. FIG. 8(b) is an oblique view of the bottom of aconventional semiconductor device as viewed from the back.

[0030]FIG. 9 is a plan view, as viewed from above and drawn such that itis possible to see through the top and view the features therebelow,showing how a shield case is attached to a semiconductor device inaccordance with the conventional art.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0031] Below, embodiments of the present invention are described withreference to the drawings.

[0032]FIGS. 1 and 2 are drawings showing the external appearance of asemiconductor device in accordance with the present invention, FIG. 1being a plan view of the semiconductor device as viewed from above, andFIG. 2 being an oblique view of the bottom of the semiconductor deviceas viewed from the back.

[0033] In forming this semiconductor device, substrate(s) 1—patternedwiring, not shown, being formed thereon—is furnished with light emittingdiode chip(s), photodiode chip(s), IC chip(s), and/or other suchchip(s), not shown; these are mounted thereon by means of die bonding,wire bonding, and/or the like; and molded resin(s) 13 is or arethereafter applied to the entirety thereof together with light-emittinglens portion(s) 11 and light-receiving lens portion(s) 12. In addition,in the present embodiment, the manufacturing method described below isemployed to form electrically conductive pattern(s) 15 for shielding atend face(s) 14 at the top of substrate 1 of the semiconductor devicehaving structure as described above; and the manufacturing methoddescribed below is employed to form a plurality of terminals 17, forconnection to the internal patterned wiring, at end face(s) 16 at thebottom of substrate 1.

[0034] By thus forming electrically conductive pattern(s) 15 forshielding at end face(s) 14 at the top(s) of substrate(s) 1 andattaching such electrically conductive pattern(s) 15 at region(s) ofground plane pattern(s) on circuit board(s) of apparatus(es) which is orare provided with such semiconductor device(s), it is possible to shieldthe semiconductor device(s) from electromagnetic noise even without useof shield case(s).

[0035] In the present embodiment, electrically conductive pattern 15 isformed from copper foil. Here, material(s) possessing good shieldingcharacteristics, e.g., gold plating, may be applied to the surface ofelectrically conductive pattern 15 (hereinafter also referred to as“copper foil pattern”). Application of gold plating will make itpossible to prevent occurrence of degradation in characteristics due tothe effects of contact resistance and/or occurrence of solder defectsdue to copper foil surface oxidation. Furthermore, application ofmaterial(s) possessing good shielding characteristics, e.g., goldplating, over the copper foil will make it possible to increasesensitivity with respect to electromagnetic noise and improve shieldingeffect (anti-electromagnetic-noise effect).

[0036] Furthermore, as shown in FIG. 3, by applying electricallyconductive adhesive(s) 18 to copper foil pattern 15 formed on end face14 at the top of substrate 1, attaching shield case(s) 2 over thisportion, and adhering and curing this thereto, the entire semiconductordevice exclusive of respective lens portions 11, 12 may be enclosedwithin shield case(s) 2. This will permit more improved shieldingeffect. Furthermore, because adhesive attachment of shield case 2 tocopper foil pattern 15 eliminates the need for shield case terminal(s)for connecting the shield case(s) to ground at the outside thereof,reduction in shield case size is made possible.

[0037] In such a case, the surface of shield case 2 may be plated withgold. This will permit further improvement in shielding effect.Furthermore, application of gold plating will make it possible toprevent occurrence of degradation in characteristics due to the effectsof contact resistance and/or occurrence of solder defects due to surfaceoxidation at copper foil pattern 15.

[0038] Furthermore, in the event that gold plating is applied to copperfoil pattern 15, and/or in the event that gold plating is applied toshield case 2, silver paste may be applied to the copper foil pattern 15portion before attaching shield case 2. Due to compatibility betweensilver paste and gold plating, this makes it possible to improveadhesive strength.

[0039] Furthermore, plurality of terminals 17 formed at end face 16 atthe bottom of substrate 1 are formed in required number, size, and shapeby using die(s) to blank out the electrically conductive pattern portionformed at end face 16 at the bottom of substrate 1 (described below atdescription of manufacturing method). As shown in FIG. 2, in the presentembodiment, terminals 17 are formed with rectangular cross-section andso as to protrude to the exterior. In such case, as shown at theenlarged view of the terminal tip portions in FIG. 4, it is possible bychamfering the corners 17 a at either side of terminal(s) 17 to increasethe surface area available for soldering by amount(s) corresponding tochamfered face(s) 17 a, i.e., by amount(s) corresponding to AS. Thispermits attainment of increased mounting strength during mounting ofsemiconductor device(s) to apparatus circuit board(s).

[0040] Next, referring to the respective process drawings shown in FIGS.5 and 6, methods of manufacturing semiconductor devices having theforegoing constitutions are described.

[0041] First, substrate 1 is prepared, a plurality of fields containingpatterned wiring being formed horizontally and vertically thereon; lightemitting diode chips, photodiode chips, IC chips, and/or other suchsemiconductor chips are incorporated into the respective patternedwiring fields of substrate 1, being mounted thereon by means of diebonding, wire bonding, and/or the like; and by thereafter using resin tomold the entirety of each together with light-emitting lens portion(s)and light-receiving lens portion(s), semiconductor device blocks(semiconductor device units) B, B, . . . are formed horizontally andvertically. Such state of affairs is shown at FIG. 5(a).

[0042] Next, as shown at FIG. 5(b), vertically long sets ofthrough-holes 31, 32, . . . are respectively formed in more or lessparallel fashion with respect to the end face portion corresponding tothe top (the end face at the left side in the drawing) of, and withrespect to the end face portion corresponding to the bottom (the endface at the right side in the drawing) of, respective semiconductordevice blocks B, B, . . . (each column of semiconductor blocks willhereinafter be referred to collectively as a “block column”) which arearranged in vertical fashion, metal plating is applied to the interiorof these through-holes 31, 32, . . . , and electrically conductivepattern 33 is formed.

[0043] Next, as shown at FIG. 5(c), blanking dies 41 are respectivelyarranged between respective sets of horizontally adjacent block columnsB1, B2, . . . .

[0044] Here, as shown in the partial enlarged view at FIG. 6(a), die 41is such that the left side face portion 41 a thereof disposed inopposition to through-holes 32 formed alongside the end face portioncorresponding to the bottoms of the blocks at block column B1 is formedafter the fashion of a comb having teeth of such number, size, and shapeas is consistent with the terminals that are to be formed; and such thatthe right side face portion 41 b thereof disposed in opposition tothrough-holes 31 formed alongside the end face portion corresponding tothe tops of the blocks at block column B2 is formed after the fashion ofa straight line lying alongside the side farther from block column B2 ofperiphery 31 a circumscribing through-holes 31 so as to blank out onlythe substrate 1 portion, leaving undisturbed the entire electricallyconductive pattern 33 applied over through-holes 31.

[0045] Moreover, as a result of using dies 41 of such shape to carry outblanking on substrate 1, block columns B1, B2, . . . are formed, asshown at FIG. 6(b), in which copper foil pattern 15 is formed at the endface portion corresponding to the top thereof, and plurality ofterminals 17, 17, . . . are formed at the end face portion correspondingto the bottom thereof. That is, simultaneous formation of copper foilpattern 15 and terminals 17, 17, . . . is permitted.

[0046] Lastly, by subjecting substrate 1, on which block columns B1, B2,. . . have thus been formed, to dicing along dicing lines L as indicatedby the dashed lines at FIG. 6(b), it is possible to divide this into theindividual semiconductor devices.

[0047] As described above, in accordance with one or more embodiments ofthe semiconductor device and manufacturing method for same of thepresent invention, by forming electrically conductive pattern(s) forshielding at end face(s) at top(s) of substrate(s) and attaching suchelectrically conductive pattern(s) at region(s) of ground planepattern(s) on circuit board(s) of apparatus(es) which is or are providedwith such semiconductor device(s), it is possible to shieldsemiconductor device(s) from electromagnetic noise even without use ofshield case(s). In such case, by applying material(s) possessing goodshielding characteristics, e.g., gold plating, over electricallyconductive pattern(s), it is possible to increase sensitivity withrespect to electromagnetic noise and improve shielding effect(anti-electromagnetic-noise effect). Furthermore, because IC circuitryfor electromagnetic noise employed as strategy in conventional productis eliminated and because shield case(s) can also be eliminated, thenumber of required circuit components can be reduced, reductions in costand in size can be achieved, and it is possible to carry out high-speedcommunication without abnormal operation despite presence ofelectromagnetic noise. Furthermore, the semiconductor device associatedwith the present invention may be favorably used in infraredcommunication devices. However, its use is not limited to infraredcommunication devices.

[0048] Furthermore, it is possible to further improve shielding effectby attaching shield case(s) over electrically conductive pattern(s) byway of intervening electrically conductive adhesive(s), and/or byapplying gold plating to surface(s) of such shield case(s). Furthermore,application of gold plating will make it possible to prevent occurrenceof degradation in characteristics due to the effects of contactresistance and/or occurrence of solder defects due to copper foilsurface oxidation.

[0049] Furthermore, by causing shape(s) of terminal(s) formed atbottom(s) of semiconductor device(s) to be formed so as to berectangular in cross-section and so as to protrude to the exterior, itis possible when mounting semiconductor device(s) to circuit board(s) ofapparatus(es) to achieve mounting such that there is good positionalaccuracy during reflow mounting due to self-alignment effect resultingfrom positional displacement. Moreover, by using die(s) to blank out andform terminal(s) into special shape(s) during formation of end face(s)at bottom(s) of semiconductor device(s), because greater copper foilsurface area can be attained at terminal end face(s) than was the caseconventionally, it is possible to increase mounting strength withrespect to apparatus circuit board(s).

What is claimed is:
 1. A semiconductor device in which one or moresemiconductor chips have been mounted onto one or more substratesincorporating patterned wiring and the entirety or entireties has orhave been sealed with one or more resins, wherein: one or moreelectrically conductive patterns for shielding is or are formed at oneor more end faces at the top of at least one of the substrate orsubstrates.
 2. A semiconductor device according to claim 1 wherein: atleast one of the electrically conductive pattern or patterns is at leastone copper foil pattern.
 3. A semiconductor device according to claim 2wherein: at least one plating having good shielding characteristics isapplied over at least one of the copper foil pattern or patterns.
 4. Asemiconductor device according to claim 3 wherein: at least one of theplating or platings is gold plating.
 5. A semiconductor device accordingto any of claims 2 through 4 wherein: one or more shield cases is or areattached over at least one of the electrically conductive pattern orpatterns by way of one or more intervening electrically conductiveadhesives.
 6. A semiconductor device according to claim 5 wherein: atleast one of the shield case or cases is gold-plated.
 7. A semiconductordevice according to claim 4 or 6 wherein: one or more shield cases is orare attached over at least one of the electrically conductive pattern orpatterns by way of one or more intervening silver pastes.
 8. Asemiconductor device in which one or more semiconductor chips have beenmounted onto one or more substrates incorporating patterned wiring andthe entirety or entireties has or have been sealed with one or moreresins, wherein: one or more electrically conductive patterns is or areformed at one or more end faces at the bottom of at least one of thesubstrate or substrates; and at least as many terminal or terminals ofsuch number, size, and shape as is or are sufficient for connection tothe patterned wiring is or are formed by using one or more dies to blankout and shape at least one region at or in the vicinity of at least oneof the electrically conductive pattern or patterns.
 9. A semiconductordevice according to claim 8 wherein: at least one of the terminal orterminals is formed so as to at least partially protrude to the exteriorand so as to have at least one more or less rectangular cross-section.10. A semiconductor device according to claim 8 or 9 wherein: at leastone gold plating is applied to at least one end face of at least one ofthe terminal or terminals.
 11. A semiconductor device manufacturingmethod comprising: forming a plurality of patterned wiring fieldshorizontally and vertically on one or more substrates, at least one ofthe fields containing patterned wiring for connection to one or moresemiconductor chips; mounting at least one of the semiconductor chips orchips to at least one of the patterned wiring fields; sealing theentirety of at least one of the mounted semiconductor chips or chipswith one or more resins; thereafter forming at least one vertically longset of at least two through-holes in more or less parallel fashion withrespect to at least one region at or in the vicinity of at least one endface at at least one side corresponding to at least one top and withrespect to at least one region at or in the vicinity of at least one endface at at least one side corresponding to at least one bottom of eachof at least one of the semiconductor chip or chips; applying plating toat least a portion of the interior of at least one of the through-holeor through-holes; forming one or more electrically conductive patterns;thereafter using one or more dies to blank out and shape at least oneregion at or in the vicinity of at least a portion of the through-holesand containing at least one region at or in the vicinity of at least oneof the electrically conductive pattern or patterns formed in at leastone region at or in the vicinity of at least one of the end face orfaces at at least one of the side or sides corresponding to at least oneof the bottom or bottoms of at least one of the semiconductor chip orchips so as to form one or more electrically conductive patterns forshielding at or in the vicinity of at least one of the end face or facesat at least one of the side or sides corresponding to at least one ofthe top or tops of at least one of the semiconductor chip or chips, andso as to form at least as many terminal or terminals of such number,size, and shape as is or are required for at least one region at or inthe vicinity of at least one of the end face or faces at at least one ofthe side or sides corresponding to at least one of the bottom or bottomsof at least one of the semiconductor chip or chips; and thereaftercutting in one or more directions perpendicular to at least one of thevertically long set or sets of through-holes so as to dividesubstantially the entirety into a plurality of individual semiconductordevices.
 12. A semiconductor device manufacturing method according toclaim 11 further comprising: attaching one or more shield cases over atleast one of the electrically conductive pattern or patterns forshielding formed at or in the vicinity of at least one of the end faceor faces at at least one of the side or sides corresponding to at leastone of the top or tops of at least one of the semiconductor chip orchips by way of one or more intervening electrically conductiveadhesives.